Combinational logic circuits are fundamental building blocks in digital electronics:
1. What is the primary characteristic of a combinational logic circuit?
Correct Answer: B) Output depends only on present inputs
Explanation: Combinational logic circuits have these key characteristics: - Output depends only on current input combination - No memory elements (no feedback) - No clock signal required - Examples: Adders, multiplexers, decoders
2. Which of the following is NOT a combinational circuit?
Correct Answer: B) Counter
Explanation: - Counter is a sequential circuit (has memory) - Counters use flip-flops to store state - Output depends on both current inputs and previous state - All other options are pure combinational circuits
3. Combinational circuits are mainly designed using which logic gates?
Correct Answer: C) Universal gates (NAND, NOR) and basic gates (AND, OR, NOT)
Explanation: Combinational circuits can be designed using: - Basic gates: AND, OR, NOT (for simple implementations) - Universal gates: NAND or NOR alone (can implement any function) - XOR/XNOR are used for specific functions like parity checking - Most designs use a combination of these gates
4. A half-adder is used to perform which arithmetic operation?
Correct Answer: A) Addition of two single-bit numbers
Explanation: Half adder characteristics: - Adds two 1-bit binary numbers (A and B) - Produces two outputs: Sum (S) and Carry (C) - Truth table: A B | S C 0 0 | 0 0 0 1 | 1 0 1 0 | 1 0 1 1 | 0 1 - Cannot handle carry input from previous stage
5. What are the logic gates used in a half-adder?
Correct Answer: A) XOR and AND
Explanation: Half adder implementation: - Sum (S) = A ⊕ B (XOR operation) - Carry (C) = A · B (AND operation) - Circuit requires 1 XOR gate and 1 AND gate - Can also be implemented using only NAND or NOR gates (universal gates)
6. How many inputs and outputs does a full adder have?
Correct Answer: C) 3 inputs, 2 outputs
Explanation: Full adder specifications: - Inputs: A, B, and Carry-in (Cin) - Outputs: Sum (S) and Carry-out (Cout) - Can add three 1-bit numbers (A+B+Cin) - Used as building block for multi-bit adders - Truth table has 8 rows (2^3 combinations)
7. The sum output in a full adder circuit is obtained using which logic gate(s)?
Correct Answer: B) XOR gate
Explanation: Full adder sum output: - Sum (S) = A ⊕ B ⊕ Cin - Requires two XOR gates in cascade - First XOR: A ⊕ B - Second XOR: (A ⊕ B) ⊕ Cin - Represents odd function (1 when odd number of inputs are 1)
8. The carry output in a full adder circuit is obtained using which logic gates?
Correct Answer: A) AND and OR
Explanation: Full adder carry output: - Cout = (A · B) + (Cin · (A ⊕ B)) - Implementation requires: 1 AND gate for A·B 1 AND gate for Cin·(A⊕B) 1 OR gate to combine both terms - Alternative implementation possible with majority function
9. A full adder can be constructed using how many half adders?
Correct Answer: B) 2
Explanation: Full adder using half adders: - First half adder adds A and B (produces S1 and C1) - Second half adder adds S1 and Cin (produces final Sum and C2) - Carry-out = C1 OR C2 - Total components: 2 half adders + 1 OR gate - More efficient implementations exist using fewer gates
10. The function of a half-subtractor is to:
Correct Answer: A) Subtract two single-bit binary numbers
Explanation: Half subtractor characteristics: - Subtracts two 1-bit numbers (A - B) - Produces Difference (D) and Borrow (Bout) - Truth table: A B | D Bout 0 0 | 0 0 0 1 | 1 1 1 0 | 1 0 1 1 | 0 0 - Cannot handle borrow input from previous stage
11. What are the logic gates used in a half-subtractor?
Explanation: Half subtractor implementation: - Difference (D) = A ⊕ B (XOR operation) - Borrow (Bout) = A' · B (AND operation with A complemented) - Circuit requires 1 XOR gate and 1 AND gate with inverter - Similar to half adder but with complemented input for borrow
12. What is the formula for the Borrow output in a half-subtractor?
Correct Answer: C) A'B
Explanation: Borrow output logic: - Borrow occurs when A=0 and B=1 - Boolean expression: Bout = A' · B - Read as "NOT A AND B" - Example cases: A=0, B=1 → Bout=1 (need to borrow) A=1, B=0 → Bout=0 (no borrow needed) A=1, B=1 → Bout=0 (no borrow needed)
13. How many inputs and outputs does a full subtractor have?
Explanation: Full subtractor specifications: - Inputs: A (minuend), B (subtrahend), Bin (borrow-in) - Outputs: Difference (D), Borrow-out (Bout) - Can subtract three 1-bit numbers (A-B-Bin) - Used as building block for multi-bit subtractors - Truth table has 8 rows (2^3 combinations)
14. Which logic gates are used in a full subtractor circuit?
Correct Answer: A) XOR, AND, OR
Explanation: Full subtractor implementation: - Difference (D) = A ⊕ B ⊕ Bin (3-input XOR) - Borrow-out (Bout) = (A' · B) + (Bin · (A ⊕ B)') - Requires: 2 XOR gates (one can be XNOR) 2 AND gates 1 OR gate 1 NOT gate (for complementing A) - Similar structure to full adder but with complemented terms
15. What is the primary function of a comparator?
Correct Answer: B) Compares two binary numbers and outputs their relationship
Explanation: Comparator functions: - Compares magnitude of two binary numbers (A and B) - Typical outputs: A > B A = B A < B - Used in control systems, arithmetic units - Can be cascaded for larger bit-width comparisons
16. A 1-bit comparator has how many inputs?
Explanation: 1-bit comparator details: - Inputs: A and B (two single-bit numbers) - Outputs: A>B, A=B, A - Simple implementation with logic gates: A>B = A · B' A=B = A ⊕ B (XNOR) A - Basis for building multi-bit comparators
17. What are the three possible outputs of a 2-bit comparator?
Correct Answer: A) Less than, Equal to, Greater than
Explanation: 2-bit comparator outputs: - A>B: When A is numerically greater than B - A=B: When both bits are exactly equal - A - Only one output is active (1) at any time - For 2-bit numbers A=A1A0 and B=B1B0, comparison is done MSB first
18. How many logic gates are used in a 2-bit comparator?
Correct Answer: C) 6
Explanation: 2-bit comparator implementation: - Requires comparison of both bits (A1A0 vs B1B0) - Typical implementation uses: 2 XNOR gates (for equality comparison) 2 AND gates (for magnitude comparison) 2 OR gates (to combine results) - More efficient implementations possible with K-map optimization - Number may vary based on specific design
19. The logic expression for equality (A = B) in a comparator is given by:
Correct Answer: D) (A ⊕ B)'
Explanation: Equality detection logic: - XOR gate gives 1 when inputs are different (A ⊕ B) - Complementing XOR gives XNOR (A ⊕ B)' - XNOR gives 1 only when both inputs are equal - For multi-bit comparators, equality is AND of all bit-wise XNORs - Example: 2-bit equality = (A1 ⊕ B1)' · (A0 ⊕ B0)'
20. A 4-bit comparator requires how many comparators for implementation?
Correct Answer: D) 4
Explanation: 4-bit comparator design: - Can be built using cascaded 1-bit comparators - Requires 4 stages (one per bit) - Modern implementations use single IC (e.g., 7485 4-bit comparator) - Comparison starts from MSB to LSB - First unequal bit determines the overall result - More efficient than using multiple 1-bit comparators