Flip-Flop MCQs

Correct Answer: b) Sequential circuit

Explanation:
Flip-flops are sequential circuits because they have memory elements and their outputs depend not only on current inputs but also on previous states.

Correct Answer: c) Storage of a single bit

Explanation:
The fundamental purpose of a flip-flop is to store one bit of digital information (0 or 1). This makes it the basic building block of sequential circuits and memory elements.

Correct Answer: b) 2

Explanation:
Flip-flops are bistable multivibrators, meaning they have two stable states: Q=1 (SET) and Q=0 (RESET). They can remain indefinitely in either state until triggered to change.

Correct Answer: c) Both a and b

Explanation:
The D flip-flop is called Data flip-flop because it stores the data present at its input. It's also called Delay flip-flop because the output is a delayed version of the input (delayed by one clock cycle).

Correct Answer: b) 1

Explanation:
In a D flip-flop, the output Q takes the value of input D at the active clock edge. When D=1 and a clock pulse is applied, Q becomes 1.

Correct Answer: a) Q⁺ = D

Explanation:
The characteristic equation of a D flip-flop is Q⁺ = D, meaning the next state (Q⁺) equals the current D input, regardless of the current state.

Correct Answer: c) SR flip-flop

Explanation:
The JK flip-flop eliminates the invalid state problem of the SR flip-flop. When J=K=1, the JK flip-flop toggles instead of entering an undefined state.

Correct Answer: d) Toggle

Explanation:
When J=K=1, the JK flip-flop toggles its state (changes to the opposite state) on the active clock edge. If Q was 0, it becomes 1, and vice versa.

Correct Answer: d) Q⁺ = JQ' + KQ

Explanation:
The characteristic equation of a JK flip-flop is Q⁺ = JQ' + K'Q, where Q' is the complement of Q. This equation describes all possible input combinations.

Correct Answer: b) JK flip-flop

Explanation:
A T flip-flop can be created by connecting both J and K inputs of a JK flip-flop together to form a single T (Toggle) input.

Correct Answer: b) Toggle

Explanation:
When T=1, the flip-flop changes state (toggles) on each active clock edge. If Q was 0, it becomes 1, and vice versa.

Correct Answer: a) Q⁺ = T⊕Q

Explanation:
The characteristic equation of a T flip-flop is Q⁺ = T⊕Q, meaning the next state is the XOR of the current state and the T input.

Correct Answer: a) To eliminate the race-around condition

Explanation:
The Master-Slave configuration prevents race-around conditions by separating the input sampling (Master) and output transition (Slave) phases using opposite clock edges.

Correct Answer: b) Uses a pair of flip-flops

Explanation:
A Master-Slave JK flip-flop consists of two flip-flops in series - the Master samples inputs on one clock edge, and the Slave updates outputs on the opposite edge.

Correct Answer: d) All of the above

Explanation:
A D flip-flop can be constructed from:
1) SR flip-flop by adding an inverter between S and R
2) JK flip-flop by connecting J to D and K to D'
3) T flip-flop by connecting T to D⊕Q

Correct Answer: a) Connect J = K = T

Explanation:
When J=K=T, the JK flip-flop behaves as a T flip-flop:
- When T=0 (J=K=0), output remains same (no change)
- When T=1 (J=K=1), output toggles

Correct Answer: b) 5 MHz

Explanation:
With J=K=1, the flip-flop toggles on each clock pulse, producing one output transition per clock cycle. Therefore, the output frequency is half the clock frequency (10 MHz / 2 = 5 MHz).

Correct Answer: b) 250 Hz

Explanation:
Each T flip-flop divides the frequency by 2:
1st flip-flop: 1 kHz → 500 Hz
2nd flip-flop: 500 Hz → 250 Hz

Correct Answer: c) 16

Explanation:
A 4-bit counter has 2^4 = 16 possible states (from 0000 to 1111 in binary). Each additional flip-flop doubles the number of states.

Correct Answer: d) 1.25 MHz

Explanation:
Each flip-flop (with J=K=1) divides the frequency by 2:
1st: 20 MHz → 10 MHz
2nd: 10 MHz → 5 MHz
3rd: 5 MHz → 2.5 MHz
Correction: The correct answer should be c) 2.5 MHz