1.1 What differentiates a sequential circuit from a combinational circuit?
Correct Answer: c) Has memory elements and depends on past inputs
Explanation: Sequential circuits differ from combinational circuits by having memory elements (like flip-flops) that allow them to store state information and make their outputs dependent on both current inputs and previous states.
1.2 Which of the following is NOT a sequential circuit?
Correct Answer: c) Multiplexer
Explanation: A multiplexer is a combinational circuit that selects one of many inputs based on control signals. Flip-flops, latches, and counters are all sequential circuits as they can store state information.
1.3 Which type of circuit is used in memory elements of digital systems?
Correct Answer: b) Sequential
Explanation: Memory elements require the ability to store information (state), which is a characteristic of sequential circuits. Combinational circuits have no memory capability.
1.4 Which of the following components is essential for designing sequential circuits?
Correct Answer: c) Flip-flop or latch
Explanation: Flip-flops and latches are the basic memory elements that provide the state storage capability required in sequential circuits. The other options are combinational circuits.
2.1 An SR latch has how many inputs?
Correct Answer: b) 2
Explanation: An SR latch has two inputs: Set (S) and Reset (R). When S is active, the output Q is set to 1. When R is active, Q is reset to 0.
2.2 What is the condition for an SR latch to be in an invalid state?
Correct Answer: c) S = 1, R = 1
Explanation: When both S and R are 1 simultaneously, the latch enters an invalid state where both outputs (Q and Q') try to be 0, which violates their complementary nature.
2.3 What happens if both inputs of an SR latch are set to 0?
Correct Answer: a) The output remains the same
Explanation: When S=0 and R=0, the SR latch maintains its previous state (no change condition). This is the memory characteristic of the latch.
2.4 Which logic gates are used to construct an SR latch?
Correct Answer: c) NOR or NAND gates
Explanation: An SR latch can be constructed using either two cross-coupled NOR gates (active-high inputs) or two cross-coupled NAND gates (active-low inputs).
2.5 An SR latch is built using NOR gates. If Q=0 and Q'=1, what will be the next state if S=0 and R=1?
Correct Answer: b) Q = 0, Q' = 1
Explanation: For a NOR-based SR latch, R=1 (with S=0) will reset the latch, making Q=0 and Q'=1 regardless of previous state.
2.6 A NOR gate-based SR latch receives an input of S = 0 and R = 1 for 10 ms. If it was initially in the Set state, what will be the final output?
Explanation: With R=1 and S=0, the latch will be in Reset state (Q=0, Q'=1). The duration (10 ms) doesn't affect the final state as long as the inputs remain stable beyond the propagation delay.
3.1 A D-latch is used to:
Correct Answer: a) Store a single bit of data
Explanation: A D-latch is a level-sensitive memory element that can store one bit of data (0 or 1) when enabled. It is commonly used for temporary data storage in digital systems.
3.2 What is the main advantage of a D-latch over an SR-latch?
Correct Answer: b) Removes the invalid state (S = 1, R = 1)
Explanation: A D-latch eliminates the invalid state problem of SR latches by using a single data input (D) that is complemented to feed both S and R inputs of an internal SR latch.
3.3 How many inputs does a D-latch have?
Correct Answer: b) 2 (D and Enable/Clock)
Explanation: A basic D-latch has two inputs: Data (D) input and Enable/Clock (E or CLK) input. When enabled, the D input is transferred to the output Q.
3.4 A D-latch stores the value of the input when:
Correct Answer: d) All of the above
Explanation: D-latches can be designed to be active-high (store when enable=1), active-low (store when enable=0), or clock-level sensitive (positive or negative level triggered).
3.5 If a D-latch operates at a clock frequency of 5 MHz, what is the duration of each clock cycle?
Correct Answer: b) 200 ns
Explanation: Clock period = 1/frequency = 1/(5×10^6) = 0.2×10^-6 seconds = 200 ns. This is the time for one complete clock cycle.
3.6 A D-latch has an input delay of 10 ns and an output delay of 15 ns. If the enable signal is given for 30 ns, how long will the output remain stable?
Correct Answer: a) 5 ns
Explanation: Total delay = input delay + output delay = 10 ns + 15 ns = 25 ns. With 30 ns enable duration, the output remains stable for 30 ns - 25 ns = 5 ns.
4.1 Which of the following is TRUE for SR and D latches?
Correct Answer: a) SR-latch can have an invalid state, but D-latch cannot
Explanation: The D-latch was specifically designed to eliminate the invalid state (S=R=1) problem of SR latches. Both basic SR and D latches are level-sensitive (not edge-triggered).
4.2 What is the main application of a D-latch?
Correct Answer: c) Data storage and transmission
Explanation: D-latches are primarily used for temporary data storage and for synchronizing data transfer between different parts of a digital system operating at different clock domains.
5.1 Which type of memory is primarily built using D-latches?
Correct Answer: b) SRAM
Explanation: SRAM (Static RAM) uses cross-coupled inverters (similar to latches) for each memory cell. DRAM uses capacitors, while ROM and Flash are non-volatile memories with different structures.
5.2 In an electronic voting machine, which type of latch is likely used for temporarily storing a vote before counting?
Correct Answer: b) D-latch
Explanation: D-latches are commonly used for temporary data storage applications like vote storage because they can hold the data until it's processed, and they don't have the invalid state issue of SR latches.